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A 32 nm node BEOL demonstrator using trench first hard mask (TFHM) architecture is realized. The dual damascene process is performed with ELK dielectric at line and via level and with an adapted metallization in order to meet ITRS specifications. ELK k=2.3 & k=2.2 are studied in a TFHM architecture in order to prove its extendibility to ELK dielectric materials.
The low field conduction mechanism in advanced Cu/ULK interconnects is consistent with 3D phonon-assisted hopping conduction in exponential band-tails. From these measurements, a defectivity parameter proportional to the density of defects near Fermi level is deduced. In addition, the relative fraction of interface versus bulk defect states may be obtained using measurements for several dielectric...
Integrated circuits are more and more impacted by interconnect performance. As size reaches nanometric dimensions, changes in materials aim at performing a reliable and compliant technology with a maximum capability to reduce delay time and power consumption. At the 32 nm node, k value reduction of existing porous SiOCH and optimization of metallization with thin barrier, conformal seed and plating...
Electrical, electrooptical, mechanical, and microstructural characterizations explain why the leakage currents in advanced Cu/ultralow-interconnects can change from bulk (3-D) to mostly interfacial (2-D) above 150degC. A physical model consistent with all these results is proposed.
The purpose of this paper is to show the role of the sidewall barrier on the nucleation / growth of electromigration induced voids in Cu interconnects. A comparison is made between an anisotropic PVD process and a conformal CVD process. Standard electromigration (EM) and scanning electron microscopy (SEM) give a clear picture of the failure mechanisms. SEM shows the steps of void growth in 120 nm...
Electrical, electro-optical, mechanical and microstructural characterizations explain why the leakage currents in advanced Cu/ultra-low K interconnects can change from bulk (3D) to mostly interfacial (2D) above 150degC. A physical model consistent with all these results is proposed
A 45nm node BEOL integration scheme is presented with 140nm metal pitch at local and intermediate levels and 70nm via size. The dual damascene (DD) process is performed in a full porous low-k (k=2.5) at line and via level in order to meet RC performance requirements. Parametrical results show functional via chains and good line resistance and serpentine continuity at 45nm node dimensions. Copper resistivity...
The spectral photoresponse of advanced interconnects is potentially interesting for the precise characterization of advanced interconnects, using standard comb test structures under illumination. This electro-optical method provides detailed information of the chemical composition of each layer of the dielectric stack via their bandgap. In addition, this non-destructive characterization is sensitive...
Patterning and ashing are known to be critical steps to the integration of porous ultra low-k dielectrics in interconnects, mainly due to low-k damage during these processes. In this paper, we investigate the impact of a new methane based ash chemistry on the sidewall modification of the porous dielectric. Physical and electrical characterizations of the integrated low-k evidence a sealing effect...
Electrical high-speed signal characterization and simulation are presented for Cu-SiO/sub 2/ on-chip wiring structure. Propagation constant, characteristic impedance and R, L, C, G matrices are extracted from frequency measurements in a whole spectrum and compared to values obtained by EM modeling. Very good agreement is reported between measured and simulated signals for propagation and crosstalk...
Integration of three level of SiO/sub 2/ air gap has been successfully achieved in a complete CMOS copper interconnect scheme. SiO/sub 2/ air gap is demonstrated to be a reliable ultra low k for sub 0.1 /spl mu/m technologies with a well controlled dielectric constant below 2.
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