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Integrated circuits are more and more impacted by interconnect performance. As size reaches nanometric dimensions, changes in materials aim at performing a reliable and compliant technology with a maximum capability to reduce delay time and power consumption. At the 32 nm node, k value reduction of existing porous SiOCH and optimization of metallization with thin barrier, conformal seed and plating...
A 45nm node BEOL integration scheme is presented with 140nm metal pitch at local and intermediate levels and 70nm via size. The dual damascene (DD) process is performed in a full porous low-k (k=2.5) at line and via level in order to meet RC performance requirements. Parametrical results show functional via chains and good line resistance and serpentine continuity at 45nm node dimensions. Copper resistivity...
Patterning and ashing are known to be critical steps to the integration of porous ultra low-k dielectrics in interconnects, mainly due to low-k damage during these processes. In this paper, we investigate the impact of a new methane based ash chemistry on the sidewall modification of the porous dielectric. Physical and electrical characterizations of the integrated low-k evidence a sealing effect...
An enhanced trench first hard mask (TFHM) backend integration architecture has been developed to facilitate straightforward ultra low-k (ULK) material insertion and to enable rapid yield learning at the 65nm technology node. Parametric, yield, reliability, and RC performance data are presented for the fully-integrated, improved TFHM 300mm ULK backend
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