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A logic compatible embedded DRAM test macro fabricated in a 65nm LP CMOS process has a 512 cells-per-BL array architecture and achieves a random access frequency and latency of 667MHz and 1.65nsec, respectively at 1.1V, 85°C. The refresh period for a 99.9% bit yield was 110μsec. Key features include an asymmetric 2T gain cell, a pseudo-PMOS diode based current sensing scheme, a half swing write BL...
We demonstrate the smallest FinFET SRAM cell size of 0.063 μm2 reported to date using optical lithography. The cell is fabricated with contacted gate pitch (CPP) scaled to 80 nm and fin pitch scaled to 40 nm for the first time using a state-of-the-art 300 mm tool set. A unique patterning scheme featuring double-expose, double-etch (DE2) sidewall image transfer (SIT) process is used for fin formation...
We present an on-chip reliability monitor capable of separating the aging effects of Hot Carrier Injection (HCI), Bias Temperature Instability (BTI), and Time Dependent Dielectric Breakdown (TDDB) with high frequency resolution. Sub-μs measurements are controlled by on-chip logic in order to avoid excessive unwanted BTI recovery during stress interruptions. Frequency shift measurement resolution of...
Circuit techniques for enabling a low power logic-compatible embedded DRAM (eDRAM) are presented. A boosted 3T gain cell utilizes preferential storage node boosting to improve data retention time and increase read margin. A regulated bit-line write scheme is equipped with a steady-state storage node voltage monitor to overcome the data `1' write disturbance problem. An adaptive and die-to-die adjustable...
We propose a novel SiGe superlattice band-gap engineered (SBE) capacitorless dynamic random access memory (DRAM) cell with the 30 nm channel by the 2D TCAD simulation. The SBE capacitorless DRAM cell used a common source structure and different metal layers for the top gate word line from the bottom gate word line to realize the 4F2 (0.0036 μm2) feature size. From the 2D TCAD simulation of the SBE...
The increasing difficulties for further scaling down of Si CMOS is bringing to the fore the investigation of alternative channel materials. Among these, III-V compound semiconductors are very attractive due to their outstanding electron transport properties. This paper briefly reviews the prospects and the challenges for a III-V CMOS technology with gate lengths in the 10 nm range.
Gain cell embedded DRAMs are twice as dense as 6T SRAMs, are logic compatible, have decoupled read and write paths providing good low voltage margin, and can drive long bitlines with gain. In this work, we present a variation study of gain cell eDRAM performance using an industrial 1.2V, 65nm low power CMOS process. Two methods are proposed to analyze eDRAM performance which can be used for designing...
We have experimentally extracted the virtual-source electron injection velocity, vx0, of various III-V HFETs at room temperature. This is the carrier velocity that matters for logic applications of these transistors. Sub-100 nm devices with ??n > 10,000 cm2/V-s exhibit vx0 in excess of 3 ?? 107 cm/s even at VDD = 0.5 V. This is over 2 times that of state-of-the-art Si devices at VDD > 1. We...
This paper proposes an energy aware and bandwidth efficient mobility support architecture which handles mobility of 6LoWPAN devices, such that the communication between it and its corresponding nodes remain undisrupted. As the 6LoWPAN devices are energy and resource constrained enabling mobility in these devices with the help of conventional host based protocols like MIPv6 is not suitable. Moreover,...
High-performance 130 nm E-mode InAs p-HEMTs is fabricated using the Ne-based ALET and the buried Pt gate technology. Results from the combination of the improved gate-to-channel aspect ratio achieved by the buried Pt gate technology show that performance of the device is remarkable and the improved carrier transport property is achieved using the ALET technology.
Research on high-k (HfO2) materials has been expanded significantly. However, MOSFETs with high-k gate dielectrics on silicon still have several problems with relatively low mobility of high-k devices in thin EOT regime compared to the universal curve. In this work, as an alternative of silicon substrate, InP and In0.53Ga0.47As has been studied. W e present the material and electrical characteristics...
This article describes a knowledge-based expert system, Talib, whose domain of expertise is in the cell layout phase of the IC design task. It applies Al techniques and has been used to design IC layouts in the circuit range of four to 86 transistors. The system is implemented in OPS5, a general-purpose rule-based language. Talib accepts as input the schematic of the proposed circuit along with the...
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