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We present a negative-resistance read scheme and write scheme for spin-torque-transfer (STT) MRAM. A negative resistance shunting an STT-MRAM cell performs a non-destructive read operation, and saves power during write compared with the conventional scheme. Measurements show an 8 ns non-destructive read-access time and an average write power savings of 10.5% for a 16 kb STTMRAM fabricated in 0.13...
This paper reports on low-power and high-speed resistive switching of a Ti-doped NiO memory, which is based on the switching mechanism of the redox reactions in a filamentary conductive path. A small reset current of less than 100 muA was achieved by controlling the gate voltage of a cell transistor, which acts as an excellent current limiter in the set operation. A fast reset time of less than 5...
In this paper, we fabricated 1T1R NiO-ReRAM test circuits based on 0.18 mum CMOS technology and observed notable suppression of Ireset by imposing current compliance Icomp using a cell transistor. Reducing the stray capacitance between Pt/NiO/Pt and the cell transistor used as a current limiter is crucial in this issue. This enabled the systematic measurement of Icomp dependence of lreset for Icomp...
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