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A highly energy efficient reconfigurable accelerator called CMA (Cool Mega-Array) is proposed. It consists of a large Processing Element (PE) array without memory elements for maintain result of ALU and configuration data, a small simple programmable micro controller for data management, and the data memory. Unlike traditional coarse grained reconfigurable processors, the power consumption for hardware...
In this letter, a magnetic-field area sensor using poly-Si micro Hall devices is reported. A matrix array of Hall devices is formed on a glass substrate using fabrication processes compatible with poly-Si thin-film transistors. Here, 3 × 3 Hall devices are arrayed every 1 × 1 mm, and the dimension of the principal part is less than 50 × 50 μm. A compensation technique of the characteristic variation...
MuCCRA-3 is a low power coarse-grained Dynamically Reconfigurable Processor Array (DRPA) for a flexible off-loading engine in various SoC (System-on-a-Chip). Similar to the other DRPAs, it has an array of processing elements (PEs), a simple coarse-grained processor, consisting of an ALU and a register file, and dynamic reconfiguration of the array enables time-multiplexed execution. DRPAs including...
A kind of image processing with a low power dynamically reconfigurable processor array (DRPA) prototype MuCCRA-3 implemented with 65 nm CMOS process will be shown. The measured power is also exhibited during execution, and compared with Xilinx Virtex-5 FPGA using exactly the same environment. The demonstration shows that more than 10 times better power efficient computation is achieved using MuCCRA-3...
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