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We describe the design of two three dimensional arithmetic units (a 3D adder and a 3D multiplier) that are implemented using through-silicon-via 3D stacking technology. Compared to their 2D counterparts, our 3D adder incurs 10.6-34.3% less delay and 11.0-46.1% less energy when the width increases from 12-bit to 72-bit; the 32 times 32 3D multiplier incurs 14.4% less delay and 6.8% less energy, according...
Radiation induced soft errors have become an important reliability concern in the sub-nanometer regime. Therefore, it is imperative to devise methods to predict the soft error rates (SER) quickly and accurately in combinational circuits. In this paper, we present a novel technique and a tool to compute the SERs of designs employing hierarchical architectures such as adders and multipliers. The technique...
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