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Recent studies showed that DRAM restore time degrades as technology scales, which imposes large performance and energy overheads. This problem, prolonged restore time (PRT), has been identified by the DRAM industry as one of three major scaling challenges.This paper proposes DrMP, a novel fine-grained precision-aware DRAM restore scheduling approach, to mitigate PRT. The approach exploits process...
A new test system was devised and used to separate the amount of floating gate (FG) charge ($Q_{\mathrm {FG}}$ ) from the oxide trapped charge ($Q_{\mathrm {OX}}$ ) generated by program-and- erase ($P\!/\!E$ ) cycles. We also extracted the pure $V_{\rm mid}$ shift caused by the generation of $Q_{\mathrm {OX}}$ , which is separated from the part of $V_{t}$ shift coming from $Q_{\mathrm {FG}}$ ...
Recent studies of BTI behavior in SRAM cells showed that for high-K metal gate stack technology, PBTI induced Vth shift in NMOS is as significant as NBTI induced Vth shift in PMOS. Previous techniques of mitigating NBTI in SRAM focus mainly on PMOS and thus lack the ability to mitigate PBTI of NMOS transistors. In this paper, we propose a novel design to recover 4 internal gates within a SRAM cell...
Due to fast technology scaling, negative bias temperature instability (NBTI) has become a major reliability concern in designing modern integrated circuits. In this paper, we present a simple and proactive NBTI recovery scheme targeting at critical and busy functional units with storage cells in modern microprocessors. Existing schemes have limitations when recovering these functional units. By exploiting...
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