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Self-boost-programming for ferroelectric-NAND (Fe-NAND) flash memory was investigated by using a miniature memory cell array, which could reduce bit-line voltages for programming. As the best performance, 0.5V bit-line-voltage programming with 10μs-pulse width was successfully demonstrated. This study indicated that the Fe-NAND flash memory can be operated by much lower power consumption than that...
The world's most downsized ferroelectric-gate field effect transistors (FeFETs) with good electrical properties were successfully fabricated, which were developed as memory cells of ferroelectric-NAND (Fe-NAND), the next generation NAND flash memory. 0.54 μm- and 0.26 μm-gate FeFETs were fabricated and characterized. The stacked gate structure of the FeFETs was Pt/SrBi2Ta2O9(SBT)/Hf-Al-O/Si. Cross-sectional...
Beyond 45 nm node transistor device transition is reviewed and the compensation for Moor??s scaling law, next generation transistor structure and material will be changed. Accordingly, the ion implanter should be changed for the suitable production efficiency and new functions. The Medium Current ion implanter energy range was changed for the total low cost performance. The Low Energy ion implanter...
A nonvolatile ferroelectric complementary metal-oxide-semiconductor (CMOS) circuit with both logic and memory functions is proposed as a new application of ferroelectric field effect transistors. The logic and memory operations of a NOT-logic ferroelectric CMOS device is demonstrated. Nondestructive readings of high and low output voltage levels of the device were performed. Data retention was measured...
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