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We systematically investigated the impact of R and C scaling to 7nm node (N7) by accounting for FEOL and BEOL holistically. Speed-power performance of plainly scaled N7 turns out to be degraded compared to previous node. BEOL wire resistance (Rwire) multiplied by logic gate input pin cap (Cpin), Rwire×Cpin, is identified as a major limiter of performance and power at N7. Reducing Cpin is crucial to...
We systematically investigated the impact of R and C scaling to 7nm node (N7) by accounting for FEOL and BEOL holistically. Speed-power performance of plainly scaled N7 turns out to be degraded compared to previous node. BEOL wire resistance (Rwire) multiplied by logic gate input pin cap (Cpin), Rwire×Cpin, is identified as a major limiter of performance and power at N7. Reducing Cpin is crucial to...
A cost competitive 20nm technology node is described that enabled industry-first 20nm cellular modem chip with 2× peak data rates vs 28nm, and 2× carrier aggregation. Process and design enhancements for layout context optimization, and continuous process improvements resulted in 18% boost in circuit performance while simultaneously achieving >30% power reduction. 3 mask local interconnect and 64nm...
With newer technology nodes, circuit/device/process codesign is essential to realize the advantages of scaling. Leveraging co-design approach based on a well-established manufacturing flow, a cost effective 28 nm 4G SOC technology has been crafted. This 28 nm design strategy uses two sets of design rules and 7 different Vt cells with optimal power gating to achieve a 2.4× increase in gate density,...
In this work we have demonstrated, for the first time, a 0.605μm2 dual core oxide (DCO) dual Vdd 8T SRAM cell in 45 LPG triple gate oxide CMOS process for use as L1 cache for high performance low leakage mobile applications. The DCO 8T SRAM operates under dual voltage supplies with write assist. Compared to traditional single-end 8T cell, DCO 8T SRAM showed the same performance with only half the...
Adiabatic logic saves energy compared to static CMOS by charging the outputs efficiently and by recovering charge from the outputs. For the most promising adiabatic logic families a four phase power-clock is used, that can be generated in an energy efficient manner by using a synchronized 2N2P LC oscillator. Different input patterns to the circuit lead to different capacitive loads seen by the oscillator...
The energy consumption of digital systems can be greatly reduced by applying adiabatic logic (AL). Making best use of AL requires a dedicated system design regarding the inherent characteristics of AL. In this paper we investigate the CORDIC architecture, that can be used for various signal processing algorithms and is preeminently suitable for AL. For fast functional testing, we propose a methodology...
The NMOS and PMOS gate cross-connected bridge rectifier has been proved an efficient way to realize the power extraction for passive RFID applications. In this paper, such a rectifier has been analyzed from its different state during the period of the RF input signal. The calculations reveal the essence of this circuit and some useful relations are calculated and plotted by MATLAB. With these relations...
A proactive routing protocol called multi-mesh tree (MMT) was developed for use in wireless ad hoc network to extend connectivity from an Internet gateway to around 20 mobile nodes in a city area. In the work presented here, we extend MMT to wireless ad hoc networks of around one hundred nodes through a clustering algorithm that is integrated into the MMT creation. The proposed scheme uses a hybrid...
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