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Using cascode cell, inductance gain boosting and source degeneration techniques in 90 nm CMOS process, a two-stage power amplifier operating at 80 GHz with a minimum chip area of 0.35 mm2 demonstrates gain of 18 dB, linear output power of 10.8 dBm, saturated power of 13.3 dBm, and PAE greater than 11.8% when the amplifier is biased at Vd = 3 V and Vg = 1 V.
A 77-83 GHz power amplifier (PA) is developed using the CPW Wilkinson power-combining technique in a 90 nm CMOS process. From the single tone power measurement, a linear power gain of 20 dB, saturated power of 12.3 dBm, and maximum PAE of 3.9% are achieved for the Wilkinson MMW PA at 80 GHz.
We have developed 90nm In0.7Ga0.3As channel HEMTs, directly measured of DC and RF characteristics, and performed microwave modeling for both 90nm Si CMOS and HEMT for benchmarking logic performance for future design layout and process improvement.
Trade-off between noise figure (NF) and input return loss (RL or |S11|) imposes a fundamental limitation on the design of low noise amplifiers (LNA) for ultra-wideband (UWB) applications. A graph-based approach using Smith Chart to achieve optimum values for both NF and input RL over the desired LNA bandwidth is presented. The proposed method and device optimization technique are systematically incorporated...
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