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Behavioral synthesis automatically compiles an electronic system-level description of a hardware design into an RTL implementation. Scheduling in behavioral synthesis is an important, sophisticated, and error-prone transformation which converts the untimed or partially timed description into a fully timed implementation. We present a scalable equivalence checking algorithm for validating scheduling...
SystemC is a system-level modeling language increasingly adopted by the semiconductor industry. Quality assurance for SystemC designs is important, since undetected errors may propagate to final silicon implementations and become very costly to fix. The errors, if not fixed, can cause major damage and even endanger lives. However, quality assurance for SystemC designs is very challenging due to their...
Direct Memory Access (DMA) interfaces are a common and important component of Hardware/Software (HW/SW) interfaces between peripheral devices and their device drivers. We present a HW/SW co-validation framework to validate DMA interface implementations of a device and its driver. This framework employs a virtual prototype of the device as a reference model and performs co-validation in two stages:...
Virtual prototypes are increasingly used in device/driver co-development and co-validation to enable early driver development and reduce product time-to-market. However, drivers developed over virtual prototypes often do not work readily on silicon devices, since silicon devices often do not conform to virtual prototypes. Therefore, it is important to detect the inconsistences between silicon devices...
Loop pipelining is a critical transformation in behavioral synthesis. It is crucial to producing hardware designs with acceptable latency and throughput. However, it is a complex transformation involving aggressive scheduling strategies for high throughput and careful control generation to eliminate hazards. We present an equivalence checking approach for certifying synthesized hardware designs in...
In this paper we present ESIDE, an integrated development environment for component-based embedded systems. It leverages component-based software engineering principles to facilitate efficient, scalable, and robust hardware/software co-design, co-simulation, co-verification, and their seamless integration. We first describe the architecture and features of ESIDE. We then discuss several design decisions...
Building highly optimized embedded systems demands hardware/software (HW/SW) co-design. A key challenge in co-design is the design of HW/SW interfaces, which is often a design bottleneck. We propose a novel approach to HW/SW interface design based on the concept of bridge component. Bridge components fill the HW/SW semantic gap by propagating events across the HW/SW boundary and raise the abstraction...
In the state-of-the-art hardware/software (HW/SW) co- design of embedded systems, there is a lack of sufficient support for architectural specifications across HW/SW boundaries. Such an architectural specification ought to capture both hardware and software components and their interactions, and facilitate effective design exploitation of HW/SW trade-offs and scalable HW/SW co-verification. In this...
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