The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
To take advantage of minimum energy consumption in sub-threshold, systems are required to have robustness to variability. In sub-threshold, exponential drain current dependence on the threshold voltage produces large sensitivities to variations. Adaptive systems are required to respond to these conditions. One adaptive method, called timing error detection (TED), eliminates traditional safety margins...
Emerging ubiquitous systems such as distributed sensor networks require ultra-low power consumption. The energy minimum and thus, the lowest possible power consumption of CMOS logic, is achieved in the sub-threshold region. The exponential dependence of the drain current on threshold voltage variations leads to increased overdesign if sub-threshold circuits are to be robust. Adaptive systems are required...
Significant demand for utlra-low power applications has provided an advantage for circuits capable of sub-threshold operation. The reduction of the supply voltage (Vdd) below the threshold voltage (VT ) of transistors, or sub-threshold, provides minimum energy consumption in digital CMOS logic. The exponential dependence of the drain current on VT variations leads to increased overdesign if sub-threshold...
In this paper, a micropower interface IC for a capacitive 3-axis micro-accelerometer implemented in a 0.25-mum CMOS process is presented. The fully-integrated sensor interface consists of a DeltaSigma sensor front-end that converts the acceleration signal into the digital domain, a decimator, a frequency reference, a clock generator for the front-end, a voltage and current reference, the required...
Presented in this paper is an noise filtering solution for a tilt compensated compass. The aim of the solution is to minimize the power consumption of filtering while still providing required characteristics. As the tilt compensation is achieved whit the CORDIC-core, it is feasible to use it to perform the filtering. By analyzing the effects of the filter coefficientspsila accuracy to the tilt compensated...
A new simple method for shifting reference image data within an analog cellular array for variable block-size motion estimation is presented. The method leads to a greatly reduced number of neighborhood connections for each cell of the array, and allows for all shifts within the Marku, J., et al, (2007) search area to be performed in a single step, with simple digital controls. The new shift circuitry,...
In a 3-axis compass, the system tilt of the sensors needs to be compensated to calculate the heading of the compass correctly. A novel tilt compensation algorithm using the CORDIC algorithm is presented. Only five 2D-CORDIC operations are needed to ac quire the heading angle from three components of magnetic and acceleration data. This can be useful in ASIC and FPGA designs where the compass data...
The paper presents a DeltaSigma sensor for a capacitive micro-accelemeter. The prototype was fabricated with a 0.25 mum CMOS technology with MIM capacitors. The silicon area of the front-end is 0.49 mm2. The chip was combined with an external plusmn2g capacitive 3-axis accelerometer on a PCB.This DeltaSigma sensor front-end IC draws 1.5 muA from a 1V supply while sampling three proof masses, each...
The presented decimator was designed to decimate a delta- sigma A/D-converter as part of a sensor-interface system for a three axis accelerometer. The sensor-interface system is designed with a very low power consumption target so the main design target for the decimator is also power consumption. Further, the area of the decimator part was a constraint limiting the design. The decimator uses three...
An evolved version of variable block-size analog motion estimation cell structure is presented. Due to the space restrictions of interconnects, used advanced variable block-size motion estimation architecture necessitates using deep-submicron design technology, which enables the dense spacing of interconnects. Therefore, a novel architecture realizing the cell structure in modern 130 nm technology...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.