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Power gating is effective for reducing leakage power. Previously, a distributed sleep transistor network (DSTN) was proposed to reduce the sleep transistor area by connecting all the virtual ground lines together to minimize the maximum instantaneous current (MIC) through sleep transistors. In this paper, we propose a new methodology for determining the size of sleep transistors for the DSTN structure...
In a 0.13 mum design environment, we design two level converters to convert signals from 0.6V and 0.8V to 1.2V, respectively, to fulfill the needs of a multi-island dual-VDD CMOS SOC. Heuristic sizing guidelines are proposed to achieve better conversion speed and lower conversion energy for both level converters
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