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Unlike HBM and MM, CDM robustness is highly dependent on IC layout and packaging. Therefore, IC companies mimic IC IO rings on IO-TEG test chips to select the most appropriate CDM protection concepts (correlation from IO-TEG to final IC??s). This publication highlights pitfalls for this approach. Ensuring consistent substrate and Vss connections drastically improve the correlation.
New insights regarding the interpretation of the VFTLP IV-curve and the fast transient current and voltage waveform data are presented. These insights are used to determine the design factors affecting the turn-on time and triggering behavior of SCRs in a 90 nm bulk CMOS technology.
This paper reviews the application of SCR-based ESD protection circuits in advanced CMOS/SOI technologies. The devices are integrated in a flexible modular circuit design technique allowing for independent optimization of key characteristics. The IC application focus is on sensitive IOs, i.e. (ultra-)thin GOX input protection and robust output driver design using SCRs. Moreover, SCR transfer and integration...
This paper introduces an SCR based ESD protection design for SOI technologies. It is explained how efficient SCR devices can be constructed in SOI. These devices outperform MOS devices by about 4 times. Experimental data from 65 nm and 130 nm SOI is presented to support this.
A local protection scheme for output drivers is presented, solving the competitive triggering issue using only a very small series (~10 Ohm) resistance. This novel solution uses an SCR that is triggered by current flowing through the driver in ESD mode.
There is a trend to revive mature technologies while including high voltage options. ESD protection in those technologies is challenging due to narrow ESD design windows, NMOS degradation issues and the creation of unexpectedly weak parasitic devices. Different case studies are presented for ESD protection based on latch-up immune SCR devices.
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