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Along with electronic products developing toward lighter, thinner, and multi-functional integration, chip scale package (CSP) has been widely used in electronic packages. Wafer level packaging (WLP) has become one dominant technology. However, applications of WLP are limited by solder joint fatigue due to stress generated by the CTE mismatch among different materials. Compliant wafer level packaging...
In recent years, a large body of statistical static timing analysis and statistical circuit optimization techniques have emerged, providing important avenues to account for the increasing process variations in design. The realization of these statistical methods often demands the availability of statistical process variation models whose accuracy, however, is severely hampered by limitations in test...
Conventionally, signal net routing is almost always implemented as Steiner trees. However, non-tree topology is often superior on timing performance as well as tolerance to open faults and variations. These advantages are particularly appealing for timing critical net routings in nano-scale VLSI designs where interconnect delay is a performance bottleneck and variation effects are increasingly remarkable...
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