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We experimentally demonstrate, for the first time, a new metallic carbon nanotube (CNT) removal technique that can be readily scaled to full-wafer-scale. Existing metallic CNT removal techniques either do not remove enough metallic CNTs, or are not VLSI-compatible, or impose very large area costs when applied to wafer-scale VLSI (up to 200%). In contrast, our new technique retains VLSI-compatibility,...
We present a new ESD compact modeling methodology using Verilog-A to enable predictive full circuit ESD simulation along with supporting hardware and failure analysis results. We also present a new ESD tool (ESTEEM) to automate the ESD design simulation and optimization flow for circuit designers. Test results show excellent simulation to hardware data correlation.
We experimentally demonstrate, for the first time, monolithic three-dimensional integrated circuits consisting of multiple (up to three) layers of monolithically integrated circuits consisting of carbon nanotube field-effect transistors (CNFET) circuits and carbon nanotube (CNT) interconnects. These experimental demonstrations are made possible through a low-temperature (< 250??C) process, presented...
Large-scale experimental data from 90 nm test chips consisting of 49,152 transistors, and experiments on 90 nm test chips containing inverter chains are used to establish: 1. A gate-oxide early-life failure (ELF, also called infant mortality) candidate transistor produces gradually degraded drive currents over time; 2. A digital circuit path consisting of a gate-oxide ELF candidate transistor experiences...
Carbon nanotube field-effect transistors (CNFETs) show big promise as extensions to silicon-CMOS because: 1) Ideal CNFETs can provide significant energy and performance benefits over silicon-CMOS, and 2) CNFET processing is compatible with existing silicon-CMOS processing. However, future gigascale systems cannot rely solely on existing chemical synthesis for guaranteed ideal devices. VLSI-scale logic...
Carbon nanotubes (CNTs) are grown using chemical synthesis. As a result, it is extremely difficult to ensure exact positioning and uniform density of CNTs. Density variations in CNT growth can compromise reliability of carbon nanotube field effect transistor (CNFET) circuits, and result in increased delay variations. A parameterized model for CNT density variations is presented based on experimental...
Circuit failure prediction is used to predict occurrences of circuit failures, during system operation, before errors appear in system data and states. This technique is applicable for overcoming major scaled-CMOS reliability challenges posed by aging mechanisms such as Negative-Bias-Temperature-Instability (NBTI). This is possible because of the gradual nature of degradation associated with such...
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