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By surmounting various obstacles across the spectrum from material synthesis to device fabrication and circuit considerations, we provide a solid foundation so that carbon-based technology can move forward towards the vision of engineering VLSI circuits, but further research is still needed to realize the material potential such as higher density CNT synthesis, better metal to CNT/graphene contacts,...
We experimentally demonstrate, for the first time, a new metallic carbon nanotube (CNT) removal technique that can be readily scaled to full-wafer-scale. Existing metallic CNT removal techniques either do not remove enough metallic CNTs, or are not VLSI-compatible, or impose very large area costs when applied to wafer-scale VLSI (up to 200%). In contrast, our new technique retains VLSI-compatibility,...
Metallic carbon nanotubes (CNTs) create source-drain shorts in Carbon Nanotube Field Effect Transistors (CNFETs) resulting in excessive leakage (Ion/Ioff < 5) and highly degraded noise margins. A new technique, VLSI-compatible Metallic-CNT Removal (VMR), overcomes metallic CNT challenges by combining layout design with CNFET processing. VMR produces CNFET circuits with Ion/Ioff in the range of...
We experimentally demonstrate, for the first time, monolithic three-dimensional integrated circuits consisting of multiple (up to three) layers of monolithically integrated circuits consisting of carbon nanotube field-effect transistors (CNFET) circuits and carbon nanotube (CNT) interconnects. These experimental demonstrations are made possible through a low-temperature (< 250??C) process, presented...
Carbon nanotube field-effect transistors (CNFETs) show big promise as extensions to silicon-CMOS because: 1) Ideal CNFETs can provide significant energy and performance benefits over silicon-CMOS, and 2) CNFET processing is compatible with existing silicon-CMOS processing. However, future gigascale systems cannot rely solely on existing chemical synthesis for guaranteed ideal devices. VLSI-scale logic...
Carbon nanotubes (CNTs) are grown using chemical synthesis. As a result, it is extremely difficult to ensure exact positioning and uniform density of CNTs. Density variations in CNT growth can compromise reliability of carbon nanotube field effect transistor (CNFET) circuits, and result in increased delay variations. A parameterized model for CNT density variations is presented based on experimental...
We demonstrate carbon nanotube field effect transistors (CNFETs) using asymmetrically-correlated carbon nanotubes (ACCNT, pronounced ldquoaccentrdquo), the first demonstration of a VLSI-compatible metallic-CNT-tolerant design methodology. ACCNT CNFETs take advantage of the asymmetric correlation of CNFETs fabricated on aligned carbon nanotubes to achieve both high Ion/Ioff (up to 5 times 104) and...
Carbon nanotube field-effect transistors (CNFETs) show promise as extensions to silicon-CMOS. Ideal CNFET circuits can potentially provide 20X energy-delay-product benefits over silicon-CMOS at the 16 nm technology node. However, several challenges must be overcome before such performance benefits can be experimentally realized. In this paper, we present a brief overview of CNFET technology, and address...
We successfully demonstrate essential components and their integration for large-scale carbon nanotube field effect transistor (CNFET) technology: 1. First demonstration of full-wafer-scale growth of directional carbon nanotubes (CNTs) on 4" single-crystal quartz wafers. 2. First demonstration of full-wafer-scale CNT transfer from 4" quartz wafers to 4" silicon wafers for integration...
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