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S-parameter test structures from a 45 nm SOI CMOS technology show total capacitance per perimeter of poly-bounded ESD diodes ranges from ~0.35-0.42 fF/mum, and silicide-block (SBLK) bounded diodes show ~15-20% capacitance reduction. Floating-body or notched-silicon tied-body Gate-Silicided GGNMOS devices show total capacitance per width of ~0.65 fF/um for thin oxide devices, and ~0.72 fF/mum for thick...
A non-self protection ESD scheme using grounded-gate, gate non-silicided (GG-GNS) drain/source silicide blocked (SBLK) ESD NFET offered in 45 nm SOI CMOS technology is presented based on a comprehensive study using the high current pulse characteristics. The results show that with a minimum SBLK width over drain/source, GG-GNS NFET can handle ~3.4 mA/mum current.
In this paper, the I/O structure described is based on a state of the art 65nm SOI technology designed for SRAM and logic applications (Leobandung et al, 2005). It is a twin-well partially depleted SOI (PDSOI) CMOS technology with gate oxide thicknesses of 1.05nm (SG) and 2.35nm (DG)
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