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Scaling the conventional CMOS transistor beyond the 45 nm generation ushers in several fundamental limitations. Control of leakage currents and sustaining electrostatic integrity while maintaining historic enhancements in performance requires such ultra-thin gate-dielectrics and heavily doped bodies that a process window sufficiently large for manufacturing might not be found. While conventional SiO...
MOSFETs were fabricated on both thick and thin epi SiGe films. An ultra thin (~ 1- 2 nm) epi Si cap grown on the SiGe layers serves to separate the Ge from the high k dielectric as well as form a SiO2 interfacial layer between the SiGe channel and the high k gate dielectric. There is evidence that this cap layer is completely oxidized during the ozone based ALD high k deposition process. Both epitaxial...
We demonstrate a new vertical (3-D) Flash memory transistor cell with nanocrystals as the floating gate on the sidewalls that can form a high-retention ultrahigh density memory array. This scalable vertical cell architecture can allow a theoretical maximum array density of 1/(4F 2), where F is the minimum lithographic pitch, thus circumventing the integration density limitations of conventional planar...
High-k/metal gate pMOSFETs were fabricated on high-quality Ge1-xCx for the first time. Ge1-xCx layers with very low RMS roughness of ~3Aring were grown directly on Si by ultra-high-vacuum chemical vapor deposition (UHVCVD), without the use of relaxed Si1-xGex virtual substrates. Ge1-xCx buried-channel (BC) and surface-channel (SC) pMOSFETs with EOT = 1.9 nm and L = 10 mum exhibited high drive currents...
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