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This paper develops a new approach to design static threshold gates with hysteresis, based on integrating each pair of pull-up and pull-down transistor networks into one composite transistor network. The new static gates are then compared to the original ones in terms of delay, area, and energy consumption. In order to compare the new gate style with the original one at the circuit level, a delay-insensitive...
This paper develops a new approach to design static threshold gates with hysteresis, based on integrating each pair of pull-up and pull-down transistor networks into one composite transistor network. The new static gates are then compared to the original ones in terms of delay, area, and energy consumption. In order to compare the new gate style with the original one at the circuit level, a delay-insensitive...
Various CMOS implementations of asynchronous NULL Convention Logic (NCL) gates have been compared in terms of area, speed, energy, power, supply voltage, and noise. Additionally, a new approach to design semi-static NCL gates has been introduced. Each gate type is used to realize a delay-insensitive 4×4 NCL multiplier and the simulation results are compared. It is shown that different realizations...
We have developed a new thin-window, n-type, low-resistivity, spiral silicon drift detector (SDD) array - to be used as an extraterrestrial X-ray spectrometer (in varying environments) for NASA. To achieve low-energy response, a thin SDD entrance window was produced using a previously developed method. These thin-window devices were also produced on lower resistivity, thinner, n-type, silicon material,...
This paper demonstrates the performance, area and supply voltage scaling advantages of a Differential Cascode Voltage-Switch Logic (DCVSL)-like design over previous methods for designing C-elements. The DCVSL-like method is then applied to the design of arbitrary NULL Convention Logic (NCL) gates, which have hysteresis state-holding capability.
This paper develops an ultra-low power design methodology for bit-wise pipelined asynchronous circuits, called bit-wise MTNCL, which combines multi-threshold CMOS (MTCMOS) with bit-wise pipelined NULL Convention Logic (NCL) systems. Compared to original NCL circuits implemented with all low-Vt and high-Vt transistors, respectively, it provides the leakage power advantages of the all high-Vt NCL implementation...
We report a comprehensive study of surface orientation, channel direction, and uniaxial strain technologies for SiGe channels CMOS. On a (110) surface, SiGe nMOS demonstrates a higher electron mobility than Si (110) nMOS. The hole mobility of SiGe pMOS is greater on a (110) surface than on a (100) surface. Both electron and hole mobility on SiGe (110) surfaces are further enhanced in a <;110>...
For the first time, we demonstrate stressor contact etch stop liner (sCESL) modulation of parasitics/external resistance in nonplanar devices. We report 17% saturation drive current enhancement in underlap doped cMOS FinFETs attributed to simultaneous lowering of RS/D via biaxial S/D stress and μo increase via effective uniaxial channel stress. Our observations imply that biaxial strain engineering...
For the first time, a set of complementary metal oxide semiconductor (CMOS) FinFET devices with two different high-k/metal gate stacks of dual work function has been integrated on the same wafer to overcome the integration complexity. Two completely different metals deposited by atomic layer deposition have been integrated in a process that includes gate stack integration and dual metal gate etch...
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