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This paper presents a fast, accurate and robust method for bottom-up extraction of analog behavioral model parameters from the corresponding transistor level netlists. The proposed Verilog-A in-loop simulation based modeling approach is generic and can estimate the parameters of the corresponding model of any given circuit using relevant test-benches, thus removing the need to implement structure...
In this paper, we present a new 3D wirelength distribution model which considers the contribution of through-silicon-via (TSV) on wirelength, die area, and power consumption. Since TSVs occupy the device layer together with active devices, the die area increases if TSVs are utilized. This area overhead, which in turn affects the wirelength, worsens due to the large size of TSVs themselves, which is...
This paper presents an accurate and fully analytical model of delay in subthreshold inverters. The model characterizes the direct connection between the input slew and output delay. It is also capable of predicting the signal slew at the inverter output. Delay and slew prediction models are used to compute delay and understand slew propagation in an inverter chain. These models can also provide insight...
In this paper we propose a methodology for energy efficient Spin-Torque-Transfer Random Access Memory (STTRAM) array design at scaled technology nodes. We present a model to estimate and analyze the energy dissipation of an STTRAM array. The presented model shows the strong dependence of the array energy on the silicon transistor width, word line voltage and row/column organization. Using the array...
Under inter-die and intra-die parameter variations, the delay of a pipelined circuit follows a statistical distribution. This paper presents analytical models to estimate yield for a pipelined design based on delay distributions of individual pipe stages. Using the proposed models, it is shown that a change in logic depth and an imbalance between stage yields can improve the design yield and the area...
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