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This paper presents a procedure of pre-characterization dedicated to the logic and timing simulation of IR-drop induced delays in a logic Block Under Test (BUT) embedded in a chip. The proposed pre-characterization is twofold: the pre-characterization of the library on the one hand and the pre-characterization of the power grid on the other hand. Both should be computed only once for a given technology...
An iterative flow to generate test sets providing high fault coverage under extreme parameter variations is presented. The generation is guided by the novel metric of circuit coverage, calculated by massively parallel statistical fault simulation on GPGPUs. Experiments show that the statistical fault coverage of the generated test sets exceeds by far that achieved by standard approaches.
Current technology scaling is leading to increasingly fragile components, making hardware reliability a primary design consideration. Recently researchers have proposed low-cost reliability solutions that detect hardware faults through software-level symptom monitoring. SWAT (SoftWare Anomaly Treatment), one such solution, demonstrated with microarchitecture-level simulations that symptom-based solutions...
The Bridge project is an EU FP6 project funded by the European commission to support the EU-China joint effort on secure and distributed cooperation between European and Chinese industrial communities such as the distributed aircraft design optimization etc. The interoperability between SIMDAT GRIA and CNGrid GOS, which enables a joint grid platform between SIMDAT and CNGRID infrastructures, is fundamental...
In this work, voltage ramp dielectric breakdown (VRDB), time dependent dielectric breakdown, (TDDB) and bias temperature instability (BTI) were conducted to evaluate the impacts of process induced interfacial defects on GOI. It is found that process induced defects near the gate oxide edges by poor adhesion of photo resist resulted in severe effective thinning; and defects near oxide interfaces by...
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