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A novel architecture aiming for ideal performance and overhead tradeoff, PVS-NoC (Partial VC Sharing NoC), is presented. Virtual channel (VC) is an efficient technique to improve network performance, while suffering from large silicon and power overhead. We propose sharing the VC buffers among dual inputs, which provides the performance advantage as conventional VC-based router with minimized overhead...
Combining the benefits of 3D IC and Network-on-Chip (NoC) schemes, provides a significant performance gain for 3D stacked architectures. In recent years, Through-Silicon-Via (TSV), employed for inter-layer connectivity (vertical channel), has attracted a lot of interest since it enables faster and more power efficient inter-layer communication across multiple stacked layers. However, the area overhead...
To continue the growth of the number of transistors on a chip, the 3D IC practice, where multiple silicon layers are stacked vertically, is emerging as a revolutionary technology. Partitioning a larger die into smaller segments and then stacking them in a 3D integration can significantly reduce latency and energy consumption. Such benefits emanate from the notion that inter-wafer distances are negligible...
In this paper, a low-cost 3D NoC architecture based on Bidirectional Bisynchronous Vertical Channels (BBVC) is proposed as a solution to mitigate high area footprints of vertical interconnects. Dynamically self-configurable BBVCs, which can transmit flits in either direction, enable a system to benefit from a high-speed bidirectional channel instead of a pair of unidirectional channels for inter-layer...
We propose a performance estimation technique for a multi-core segmented bus platform, SegBus. The technique enables us to assess the performance aspects of any specific application on a particular platform configuration, modeled in Unified Modeling Language (UML). We present methods to transform Packet Synchronous Data Flow (PSDF) and Platform Specific Model (PSM) models of the application into Extensible...
Three-dimensional integrated circuits (3-D ICs) outperform traditional planar ICs in terms of performance, packaging density, interconnection power consumption, and functionality. Since the performance of 3-D ICs employing Through Silicon Vias (TSVs) depends on vertical interlayer interconnects, in this paper we present a high-performance bus architecture for TSVs.
As the size of NoCs increases, power consumption and fault/variation tolerance have become two of the most crucial problems for system designers. To address these problems, we propose a NoC architecture based on a hierarchy of monitoring agents. By tracing the circuit properties at run time, the agents at different architectural levels are able to monitor and control over the whole NoC platform. This...
System-level exploration of run-time power clusterization for energy-efficient on-chip communication is presented. Facilitated by multiple on-chip power-delivery-networks, areas of heavy or low traffics can be dynamically identified and adaptively supplied with new power schemes. This method is superior to design-time voltage island partitioning, in dealing with unpredictable spatial and temporal...
This paper presents quantitative analysis of monitoring interconnect architecture alternatives in hierarchical agent-based NoC platform. Hierarchical monitoring design methodology provides scalable dynamic management services with agents monitoring different levels. To enable low-latency and low-energy agent communication, we examined three interconnect alternatives: TDM-based virtual channeling,...
Adopting the bio-inspired system architecture, a hierarchical agent monitoring NoC design method is proposed. Based on circuit conditions traced at the run-time, system settings including resource utilization and power supplies are configured hierarchically and adaptively at each architecture level by corresponding agents. This methodology provides systematic design approaches to VLSI circuits under...
An ASIC-design-based configurable SOC architecture, which is high performance, flexible, programmable, and compiler-independent, is designed for networked media applications. A coarse-grained parallel computing mechanism is employed in this architecture. Mapping this architecture to a specific application is demonstrated through an example in multimedia application. The design is validated in a powerful...
We approach the construction of design methodologies for on-chip multiprocessor platforms, with the focus on the SegBus, a segmented bus platform. We study how applications can be mapped on such distributed architecture and show how to build the concrete level software procedures that will coordinate the control flow on the platform. The approach employs models developed in the Matlab-Simulink environment...
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