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We report a novel approach to enable the fabrication of dielectric isolated FinFETs on bulk substrates by bottom oxidation through STI (BOTS). BOTS FinFET transistors are manufactured with 42nm fin pitch and 80nm contacted gate pitch. Competitive device performances are achieved with effective drive currents of Ieff (N/P) = 621/453 µA/µm at Ioff = 10 nA/µm at VDD = 0.8 V. The BOTS process results...
2D nanoelectronics based on single-layer MoS2 offers great advantages for both conventional and ubiquitous applications. This paper discusses the large-scale CVD growth of single-layer MoS2 and fabrication of integrated devices and circuits for the first time. Fundamental building blocks of digital electronics, such as inverters and NAND gates, are fabricated to demonstrate its capability for logic...
High-performance strain-engineered ETSOI devices are reported. Three methods to boost the performance, namely contact strain, strained SOI (SSDOI) for NFET, and SiGe-on-insulator (SGOI) for PFET are examined. Significant performance boost is demonstrated with competitive drive currents of 1.65mA/µm and 1.25mA/µm, and Ieff of 0.95mA/µm and 0.70mA/µm at Ioff =100nA/µm and VDD of 1V, for NFET and PFET,...
Twisted direct silicon bonded (DSB) substrate demonstrates a higher hole mobility advantage over (110) bulk substrate for PFET. The mobility shows a (110) layer thickness dependence with the thinner DSB layer having a higher hole mobility. 25% on-current improvement is obtained for thin DSB PFETs at long channel (Lg= 2 mum), 10% higher at short channel (Lg = 36 nm) compared to (110) bulk PFETs. Moreover,...
We report on the ESD performance of dual well and triple well, silicide-blocked stacked NMOSFETs in a 45 nm CMOS technology. Triple well stacked NMOSFETs have a 1.5X higher HBM failure voltages compared to dual well designs. Further, we report on the effect of gate-biasing on the ESD performance of dual well, gate-silicided, silicide-blocked 2.5 V stacked NMOSFETs. For gate voltages (VGS) larger than...
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