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A PWM ADSL2+ line driver with 2.2 MHz signal bandwidth is realized in a 3 metal, 2 poly 0.35 mum CMOS process. A low 8.832 MHz switching frequency is used with filtering in the feedback path to suppress aliasing. Signal processing and triangular wave generation are combined in the forward integrators. The driver delivers 100 mW to a 100 Omega line with an MTPR less than -52 dB. Active area is 3 mm...
A 0.5mum CMOS chip contains a 5th-order continuous-time filter, a low output-impedance driver, and an active rectifier. The chip boosts the selectivity of an external passive LC LPF and achieves an ADSL isolation of 70dB at 30kHz, while maintaining a passband flatness of 0.23dB. It consumes 35mW from a 5V supply and reduces the number of transformers and the size of POTS/ADSL splitters
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