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Atomistic modeling and optimized TCAD simulation strategy for Laser-only annealing device are shown. Multiple laser annealing scans are modeled by using atomistic KMC. KMC clarified that dopant diffusion is changed as a function of laser scan number. SSRM with 1 nm special resolution is used for the 2-dimensional carrier distribution measurement and dopant active level determination. It is shown that...
We discuss several advancements over our previous report (S. Kubicek, 2006): - Introduction of conventional stress boosters resulting in 16% and 11% for nMOS and pMOS respectively. For the first time the compatibility of SMT (stress memorization technique) with high-kappa/metal gate is demonstrated. In addition, we developed a blanket SMT process that does not require a photo to protect the pMOS by...
n-type dopant diffusion during sub-millisecond (ms) non-melt laser annealing (NLA) is investigated through the experiments and atomistic KMC modeling. Laser-only annealing can improve the n-type dopant activation and achieve shallow junctions. KMC model with vacancy complexes indicates that laser-only annealing for nFET can achieve highly activated junctions and reduce dopant fluctuations in the channel...
A gate-first process was used to fabricate CMOS circuits with high performing high-K and metal gate transistors. Symmetric low VT values of plusmn 0.25 V and unstrained IDSAT of 1035/500 muA/mum for nMOS/pMOS at IOFF=100nA/mum and |VDD|=1.1 V are demonstrated on a single wafer. This was achieved using Hf-based high-k dielectrics with La (nMOS) and Al (pMOS) doping, in combination with a laser-only...
A thermo-mechanical stress model (TMS) is presented to explain the impact of sub-melt laser anneal (LA) on SiON dielectric and on the overall transistor performance. An Lgmin reduction of 15nm/5nm for nMOS/pMOS over our poly-Si/SiON reference, with 8% capacitance and 10% source and drain resistance (RSD) improvement, is demonstrated. Best device performance and NBTI immunity are reached by lowering...
We demonstrate for the first time the integration of metal gate electrode and non-melt laser annealed junctions in both NMOS and PMOS transistors. We report the highest drive current so far in laser annealed devices with good short channel effects (SCE) control down to 40nm gate length. Overlap length is quantified by CV and SSRM, values of 2 nm for both NMOS and PMOS laser-annealed transistors are...
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