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As the microelectronics technology continuously scales down, the probability of multiple cell upsets (MCUs) induced by radiation in memory devices increases. It is required a robust error correction code (ECC), that has also an area, energy-efficient silicon implementation, to protect electronic devices from MCUs. This article describes the conception, implementation, and evaluation of a new algorithm...
As the scale of integration of digital circuits increases, there is a corresponding increase in the probability of permanent failures in NoCs. As a result, it is essential that NoCs have fault tolerance mechanisms in order to cope with this issue. In this article, we present a NoC architecture for a fault-tolerant multiprocessor chip based upon the use of backup paths which are external to the router,...
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