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We report record breaking values for PMOS source drain (S/D) contact resistivity, ρc < 10−9Ω·cm2. These were obtained by shallow Ga ion implantation on Si0.4Ge0.6 in combination with subsequent pulsed nanosecond laser anneal (NLA). Cross section transmission electron microscopy (XTEM) shows the pc reduction mechanism is based on Ga and Ge segregation towards the surface.
We report on Atomic Layer Deposition Titanium (ALD Ti) for FinFET source/drain contact applications. On planar test structures, we accurately benchmark contact resistivity (ρc) of ALD Ti, ∼1.4×10–9 Ω·cm2 on Si:P and ∼2.0×10–9 Ω·cm2 on SiGe:B, among to lowest reported values in literature. Ultralow ρc is resulting from enhanced Ti/Si(Ge) reactivity originating in the ALD process. We also demonstrate...
Record-low contact resistivity (pc) for n-Si, down to 1.5×10−9 Q-cm2, is achieved on Si:P epitaxial layer. We confirm that Ti silicidation reduces the pc for n-Si, while an additional Ge pre-amorphization implantation (PAI) before Ti silicidation further extends the pc reduction. In situ doped Si:P with P concentration of 2×1021 cm−3 is used as the substrate, and dynamic surface anneal (DSA) boosts...
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