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Laterally actuated nanoelectromechanical (NEM) relays are implemented using a polysilicon structural layer with hafnium oxide (HfO2) and platinum dual sidewall layers. Atomic layer deposition (ALD) HfO2 provides electrical isolation between the polysilicon beam structure and the sputtered platinum conductive channel. Dual sidewall devices are demonstrated using a Y-shaped device with two contacts...
This paper presents low-voltage, high-aspect-ratio scaled lateral electrostatic actuators based on a four-mask multi-spacer process. The set of TEOS spacers, polysilicon hardmask, and buffer LTO layer is chosen as masking materials, resulting in a multi-spacer of LTO-TEOS and a stack of LTO-polysilicon hardmask. These mask sets with a photoresist mask are then transferred to an underlying polysilicon...
This paper presents a four-mask fabrication process of lateral nanoelectromechanical (NEM) electrostatic actuators based on spacer technology. Critical dimensions of the actuators, i.e., the beam width and the gap size between the movable and fixed electrodes can be made smaller than the lithographic resolution by creating nitride spacers on an oxide hardmask followed by selective etching of the oxide...
We experimentally demonstrate, for the first time, a new metallic carbon nanotube (CNT) removal technique that can be readily scaled to full-wafer-scale. Existing metallic CNT removal techniques either do not remove enough metallic CNTs, or are not VLSI-compatible, or impose very large area costs when applied to wafer-scale VLSI (up to 200%). In contrast, our new technique retains VLSI-compatibility,...
Metallic carbon nanotubes (CNTs) create source-drain shorts in Carbon Nanotube Field Effect Transistors (CNFETs) resulting in excessive leakage (Ion/Ioff < 5) and highly degraded noise margins. A new technique, VLSI-compatible Metallic-CNT Removal (VMR), overcomes metallic CNT challenges by combining layout design with CNFET processing. VMR produces CNFET circuits with Ion/Ioff in the range of...
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