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The recently proposed three-dimensional (3D) integration promises to enhance the system performance. However, it poses several test challenges. Thermal safety of the 3D system is the foremost concern. Testing of the system plays an important role to improve the yield. This work presents a thermal-aware core test scheduling technique in 3D stacked multicore system using Particle Swarm Optimization...
This brief proposes an on-line transparent test technique for detection of latent hard faults which develop in firstinput first-ouptput buffers of routers during field operation of NoC. The technique involves repeating tests periodically to prevent accumulation of faults. A prototype implementation of the proposed test algorithm has been integrated into the router-channel interface and on-line test...
This paper presents a test infrastructure development and test scheduling strategy for 3D-SICs under resource (test pins and TSVs) and power constraints. Depending upon the various scheduling restrictions, two test scheduling strategies have been proposed with an objective to minimize the overall test time (TT) of the stack. A step-by-step approach deals with the individual dies separately and develops...
With the increasing complexity of VLSI circuits and systems, their testing is becoming increasingly complex and time consuming. Apart from affecting the design turn-around time, it poses severe challenges to the test engineers in terms of meeting the power-budget and temperature limit of the chip. Power consumption during test is often much higher than in normal mode of operation. Increasing temperature...
The temperature of a block (a region in the chip) depends on both heat generation (caused by power consumption) and heat dissipation among neighbors. Power aware test solutions targeting low power consumption during testing, may not produce an acceptable thermal aware solution. In this paper, a hardware based solution using an AND-OR block between the decompressor and each scan chain, has been utilized...
This paper presents a test architecture optimization and test scheduling strategy for TSV based 3D-Stacked ICs (SICs). A test scheduling heuristic, that can fit in both session-based and session-less test environments, has been used to select the test concurrency between the dies of the stack. The proposed method minimizes the overall test time of the stack, without violating the system level resource...
With rapid progress in VLSI technology, temperature during testing has become a big issue. As increase in temperature during testing causes permanent or temporal damage of the chip, reduction in peak temperature of the chip becomes necessary. Temperature depends on both heat generation caused by power consumption and heat dissipation among neighboring blocks in the circuit under test (CUT). Heat generation...
In the sub 70 nm technologies, the leakage power dominates dynamic power. Most of the power calculation methods account for dynamic power dissipation and static leakage power dissipation, but the runtime leakage is generally neglected. It has been shown in recent studies that the contribution of runtime leakage power to the total power dissipation is not negligible any more. The dynamic power dissipation...
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