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Recently, a transistor level dual-Vth technique has been proposed, where transistors within the same cell are allowed to have different Vth to form the so-call mixed Vth (MVT) cell. However, it is impractical to build a full MVT cell library and include it in the standard dual Vth design flow. To make this practical, current approach adds another design phase after technology mapping to replace high...
In this paper, we study the interdependency between leakage energy and chip temperature in real-time systems. We observe that the temperature variation on chip has a large impact on the system's leakage energy. By incorporating the temperature information, we propose an online temperature-aware leakage minimization algorithm for real-time systems. The basic idea is to run tasks when the system is...
Input vector control (IVC) is a popular technique for leakage power reduction. It utilizes the transistor stack effect in CMOS gates by applying a minimum leakage vector (MLV) to the primary inputs of combinational circuits during the standby mode. However, the IVC technique becomes less effective for circuits of large logic depth because the input vector at primary inputs has little impact on leakage...
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