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A direct-conversion transceiver including base-band amplifiers and filters employs a 60-GHz quadrature VCO and a feedforward divider with no buffers to achieve a low power consumption. Designed in 40-nm LP CMOS, the radio presents a noise figure of 4.8 to 8.2 dB in the receive mode and an output power of +10 dBm in the transmit mode while drawing 56 mW and 124 mW, respectively.
A high performance 22/20nm CMOS bulk FinFET achieves the best in-class N/P Ion values of 1200/1100 μA/μm for Ioff=100nA/μm at 1V. Excellent device electrostatic control is demonstrated for gate length (Lgate) down to 20nm. Dual-Epitaxy and multiple stressors are essential to boost the device performance. Dual workfunction (WF) with an advanced High-K/Metal gate (HK/MG) stack is deployed in an integration-friendly...
This paper presents performance evaluation of high-kappa/metal gate (HK/MG) process on an industry standard 45 nm low power microprocessor built on bulk substrate. CMOS devices built with HK/MG demonstrate 50% improvement in NFET and 65% improvement in PFET drive current when compared with industry standard 45 nm Poly/SiON devices. No additional stress elements were used for this performance gain...
This work describes the first multiband WCDMA/HSPA/EGPRS single-chip transceiver with GPS and receiver diversity. This device supports UMTS bands 1,2,3,4,5,6,8,9,10 and GSM/EDGE 800, 900, 1800, 1900 MHz bands. It is implemented in cost-effective 0.18 mum RF CMOS technology and uses a reduced number of TX and RX SAW filters.
For the first time, we have demonstrated a 32 nm high-k/metal gate (HK-MG) low power CMOS platform technology with low standby leakage transistors and functional high-density SRAM with a cell size of 0.157 mum2. Record NMOS/PMOS drive currents of 1000/575 muA/mum, respectively, have been achieved at 1 nA/mum off-current and 1.1 V Vdd with a low cost process. With this high performance transistor,...
This paper presents a novel topology of the CMOS active bandpass filter (BPF) at C-band. The parallel resonators in the BPF are realized by the monolithic synthetic quasi-TEM transmission line (TL), the so-called complementary conducting strip transmission line (CCS-TL). The characteristics of the CMOS monolithic CCS-TL are investigated by a series of experiments. The characteristics of the CCS-TL,...
This paper presents a novel two-stage low dropout regulator (LDO) that minimizes output noise via a pre-regulator stage and achieves high power supply rejection via a simple subtractor circuit in the power driver stage. The LDO is fabricated with a standard 0.35mum CMOS process and occupies 0.26 mm2 and 0.39mm2 for single and dual output respectively. Measurement showed PSR is 60dB at 10kHz and integrated...
The CMOS transceiver IC uses the superheterodyne architecture to implement a IEEE 802.11g RF front-end with auto I/Q calibration function. 1/spl deg/ quadrature mismatch and 0.1 dB gain mismatch can be achieved after the auto tuning in both the transmitter and receiver sides. Implemented in a 0.25 /spl mu/m CMOS process with 2.7 V supply, the transceiver achieves a 5.1 dB receive cascade NF and a...
A high performance dielectric based antifuse field programmable gate array (FPGA) process has been developed using a standard 0.8 mu m double layer metal CMOS process. The process requires two additional self-contained modules to implement both the programmable interconnect element and the high voltage transistors required to program the antifuses. The antifuse is 8.4 nm ONO dielectrics. The high...
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