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In this paper, we propose a novel architecture for IDMA system with low latency and high throughput for the uplink multi-user wireless system. The throughput of the proposed IDMA system can be improved to about double compared to the conventional IDMA system while the hardware complexity remains unchanged. To achieve this, the proposed system utilizes the interleaver/de-interleaver-less architecture...
This paper demonstrates the impact of transceiver impairments on channel capacity and bit-error-rate (BER) performance of a dual-hop half-duplex cognitive relay network over AWGN channel. We consider the soft-information-relaying (SIR) protocol where the relay node computes the reliabilities (soft) of the received signal from source and then forwards to the destination. The hardware impairment model...
This paper analyzes the impact of transceiver impairments on outage probability (OP) and throughput of decode-and-forward two-way cognitive relay (TWCR) networks, where the relay is self-powered by harvesting energy from the transmitted signals. We consider two bidirectional relaying protocols namely, multiple access broadcast (MABC) protocol and time division broadcast (TDBC) protocol, as well as,...
This demo presents the verification framework for very large scale SoC System using Synopsys HAPS platform. The IEEE 802.1 lac WLAN system is selected as a case study for verification purpose. The HW/SW co-verification is carried out to confirm the feasibility of proposed system, to test data flow, and to early verify HW-SW integration. Some user experiences are also offered by proposed system such...
In Multiple Input Multiple Output (MIMO) decoders, soft decision in the form of Log Likelihood Ratio (LLR) is often used to enhance the error correction probability of the Forward Error Correction (FEC). In order to compute the LLR, the zero's probability and the one's probability of an information bit must be known. In case of using the K-best maximum likelihood detection (MLD), only a subset of...
The impairments of hardware in physical transceivers are proven to degrade the performance of wireless systems severely; however, their effects on cognitive relaying networks have not been investigated yet. In this paper, the impacts of hardware impairments in cognitive decode-and-forward (DF) network are quantified. More specifically, the exact signal to noise-and-distortion ratio (SNDR) of the relay...
This paper presents an implementation of a low complexity Wavelet OFDM system based on Haar function. The OFDM transmitter generates the orthogonal signals, and the OFDM receiver detects the signals. The idea of low complexity is the arrangement and the multistage calculations of coefficients. It was shown that the number of multiplier and adder was reduced. Hardware model presented is scalable to...
In this paper, we present an efficient and high throughput hardware implementation of the RC4 algorithm. The main idea of the proposed architecture is the utilization of a tri-port RAM to reduce the memory resource and to increase throughput. The proposed design requires two clock cycles for generating one byte of ciphering key and uses only a block of 256 bytes RAM. These result in 50% increment...
This paper shows the design and ASIC implementation of a 802.11n WLANs 4×4 MIMO OFDM PHY transceiver. The system supports the maximum data rate of 600Mbps. The MMSE-SQRD SIC MIMO decoder scheme, which has high BER performance and acceptable hardware cost, is implemented. To meet the required high throughput rate, parallel processing Scrambler/Descrambler, parallel processing BCC, and radix-4 soft-decision...
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