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Low power efficient digital devices are target of researchers in recent years. This aim attracted researchers to focus on the reversible digital circuit design approach. In ideal situations reversible circuits generate zero power loss with improved performance. Reversible circuit design approach is increasingly applied in the area of DNA computing, low power CMOS design, nanotechnology, quantum computing...
Body contacted (BC) core logic/high speed (HS) and input/output (I/O) SOI PMOSFETs from 65 nm technology are shown to have higher degradation than the counterpart floating body (FB) devices under NBTI stress. It is also observed that concurrent HCI-NBTI (hot-carrier injection-negative bias temperature instability) leads to worst case degradation for the I/O and HS SOI p-channel MOSFETs. I/O PMOS devices...
A comprehensive study on the interaction between ESD, NBTI and HCI on silicide blocked (SBLK) PFET devices is presented for a state-of-the-art 65nm bulk technology. ESD behavior of thin and thick oxide devices are shown to have opposite channel length dependence. The study of NBTI-ESD interaction on thin oxides devices shows that non-destructive ESD pre-stressing worsens the NBTI degradation. On the...
In this review, the following reliability concerns: hot carrier reliability, negative-bias temperature instability (NBTI), time depended dielectric breakdown (TDDB) and electrostatic discharge, are discussed individually, and recognizing that the responsible mechanisms quite often are active simultaneously, their interdependence and interaction is also discussed
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