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This paper presents a detailed experimental study of the electrical characteristics of long-channel ultra-thin body SOI MOSFETs with standard and thin buried oxides and high-k gate dielectric, using an analysis of the transconductance, gate-to-channel capacitance and mobility behaviors at different back-gate biases. The emphasis is on the evolution of the effective mobility when shifting the conduction...
This paper aims at presenting a detailed and comprehensive study of the influence of space-charge condition at the substrate/BOX interface, as a function of the gate length and substrate bias, on both the front threshold voltage (Vthf) and subthreshold slope (S), for sub-32nm Ultra-Thin Body (UTB) SOI MOSFETs with two different BOX thicknesses: either standard 145nm (UTB) or thin 11.5nm (UTB 2...
This paper presents a complete study of the impact of mechanical stress on the performance of SOI MOSFETs. This investigation includes dc, analog and RF characteristics. Parameters of a small-signal equivalent circuit are also ex- tracted as a function of applied mechanical stress. Piezoresistance coefficientis shown to be a key element in describing the enhancement in the characteristics of the device...
At zero-temperature-coefficient bias points, transistors are known to have stable DC performance with temperature variation. In this work, the RF behavior at those specific bias points is presented in order to provide design guidelines for low-power low-voltage circuits featuring stable RF performance in variable temperature environments and applications. Fully- and partially depleted SOI MOSFETs...
This work investigates the possibility to tune the zero-temperature-coefficient (ZTC) points in partially depleted (PD) SOI nMOSFET technology by controlling the body-source forward bias (VBS). Measured transconductance and drain current in the saturation region at temperatures between 25 and 200degC were observed for various body-source forward bias conditions. It is found that the variation of threshold...
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