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Tunnel FETs (TFETs) have been identified as the most promising steep slope devices for ultralow power logic circuits. In this paper, we demonstrate in-plane InAs/Si TFETs monolithically integrated on Si, using our recently developed template-assisted selective epitaxy approach. These devices represent some of the most scaled TFETs with dimensions of less than 30 nm, combined with excellent aggregate...
This presentation describes the challenges and recent progress toward the most prominent candidates for becoming the next nanoelectronic switch where new materials, architectures and devices are crucial.
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