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In this paper, we propose a subthreshold SRAM cell structure which can be read differentially. The main advantage of the cell is its high read current while the static noise margin and power consumption are reasonable. The cell is suitable for high performance applications where the speed is of prime concern. To assess the efficiency of the proposed cell, we compare its characteristics to three subthreshold...
In this paper, an analytical model for the HCI induced trap generation in the gate oxide and the degradation of a triple gate bulk FinFET is presented. The model which is obtained by solving the reaction-diffusion equations multi-dimensionally, includes the geometry dependence of the time-exponent of HCI degradation of the structure. In this framework, the electric field distribution and the maximum...
In this paper, a comparison between CNFET and Si-MOSFET SRAM cells at 32 nm technology node are presented. The designs are based on predictive technology model (PTM) for the Si-MOSFET cell and CNFET Stanford model for the CNFET cell. For practical reasons, in the CNFET case, the substrate of the entire chip is considered to be one node. The effect of the voltage of this node on improving the overall...
In this paper, we investigate the performance characteristic of CNFET inverter based on a new compact model. We consider temperature variation effects on the CNFET circuit performance implemented in a 32-nm technology. The results show in contrast to MOSFET sub-threshold current reduces in CNFET with temperature. So by using CNFET in high temperature applications we can obtain high speed and low leakage.
In this paper, an efficient non-iterative approach for calculating the threshold voltage of the nanoscale double gate nMOSFET is presented. First, it is shown that the parabolic potential is a reasonable approximation for the body potential along the coordinate normal to the interfaces at the threshold of conduction. Then, the energies of confined carriers are determined by solving the Schrodinger's...
In this paper, an analytical model for negative bias temperature instability (NBTI) induced degradation in a triple gate MOSFET is presented. The model is obtained by solving the reaction-diffusion equations multi-dimensionally. The formulation considers the molecular diffusion of hydrogen in the oxide. The geometry dependence of the time exponent of NBTI degradation in triple gate MOSFETs are modeled...
In this work, the effect of negative bias temperature instability (NBTI) on the potential distribution and degradation of floating-body (FB) undoped double-gate (DG) MOSFETs is modeled. The approach is based on solving the one-dimensional (1-D) Poisson's equation considering the NBTI effect in the inversion region. The study includes different stress voltages and device body thicknesses. The accuracy...
In this paper, we present a fast yet accurate semi-analytical model for the I-V and C-V characteristics of nanoscale undoped symmetric double gate (DG) MOSFETs. The model employs a simple parabolic potential approximation for the body potential in the coordinate normal to the interfaces in the all regions of operation. To include quantum effects in the model, the Schrodinger's equation is analytically...
In this paper, we propose 4T FinFET SRAM cells which are robust against NBTI effect. The cells, which only use NMOS or PMOS transistors in their structures, are called 4TLLFBNO and 4TDLFBPO, respectively. The simulation results at iso-area design reveal that 4TLLFBNO has the highest read current and 4TDLFBPO has the least power consumption among different cells. Both cells are expected to be robust...
In this paper, two static random access memory (SRAM) cells that reduce the static power dissipation due to gate and subthreshold leakage currents are presented. The first cell structure results in reduced gate voltages for the NMOS pass transistors, and thus lowers the gate leakage current. It reduces the subthreshold leakage current by increasing the ground level during the idle (inactive) mode...
On-chip MOS decoupling capacitors (DECAPs) are widely used to reduce power supply noise. Designing DECAP in nanotechnology designs provides many challenges. In this paper first it is shown that all of these challenges are functions of the DECAP channel length. Then, we propose a method for optimizing the channel length of MOS DECAPs. The technique is applied to 45 nm and 32 nm technology nodes and...
In this paper, we investigate the temperature dependence of delay propagation characteristic of FinFET circuits. The study is performed on several digital circuits including inverter, NAND, NOR, XOR and full-adder implemented in a 32-nm FinFET technology. The results show that the speed of the FinFET circuits is enhanced when the temperature is increased. The temperature dependencies of the FinFET...
In this paper, an analytical model for the threshold voltage of FinFETs is proposed. The model is derived by approximating the 2D Poissonpsilas equation by a 1-D equation. Also, in the model, a coefficient denoted by H, is used to modify the estimated value of the gate capacitance. To assess the accuracy of the model, the model results are compared by those of the numerical simulations of the device...
In this paper, a statistical approach for the optimal design of 6-T FinFET based SRAM cells considering the statistical distributions of gate length and silicon thickness of its transistors is presented. The corresponding statistical correlations of these two parameters are also considered. In this method, proper back-gate voltages for the SRAM transistors which maximize the yield against read, write,...
In this paper, we propose low power and robust 6T SRAM cells. The cells are based on the Vt-control of the cross-coupled inverters of the SRAM cell to reduce leakage power when SRAM is in the idle mode. Using the Vt-control method along with the built-in feedback leads to increasing the SNM. In comparison to a previous work, our schemes have a higher static noise margin (SNM) and lower standby power...
In this paper, a model for SOI MOSFETs which considers the self-heating effect is proposed. The model which is based on a multi layer perceptron (MLP) neural network, generates the drain current as a function of the gate-source voltage, drain-source voltage, and the device temperature. Based on the current, the temperature of the device channel is calculated. The neural network adapts itself with...
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