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Process variation as a major concern in the current and future generations of CMOS circuits manufacturing has imposed a great deal of effort in design process. Basically, process variations are generally divided in two main categories: random variations and systematic variations. Therefore, physical designers of integrated circuits (ICs) have to take into account the effects of random and systematic...
Designing MOS decoupling capacitors (DECAPs) in nanotechnologies provides many challenges due to the existing trade-offs among transient time response behavior, area, and gate leakage current. In this paper first it is shown that all of these challenges are functions of the MOS DECAP channel length. Then, we propose a method for optimizing the channel length of MOS DECAPs. The technique is applied...
In this paper, we propose low power and robust 6T SRAM cells. The cells are based on the Vt-control of the cross-coupled inverters of the SRAM cell to reduce leakage power when SRAM is in the idle mode. Using the Vt-control method along with the built-in feedback leads to increasing the SNM. In comparison to a previous work, our schemes have a higher static noise margin (SNM) and lower standby power...
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