The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Process variation as a major concern in the current and future generations of CMOS circuits manufacturing has imposed a great deal of effort in design process. Basically, process variations are generally divided in two main categories: random variations and systematic variations. Therefore, physical designers of integrated circuits (ICs) have to take into account the effects of random and systematic...
In this paper, we propose a subthreshold SRAM cell structure which can be read differentially. The main advantage of the cell is its high read current while the static noise margin and power consumption are reasonable. The cell is suitable for high performance applications where the speed is of prime concern. To assess the efficiency of the proposed cell, we compare its characteristics to three subthreshold...
In this paper, a statistical approach for the optimal design of 6-T FinFET based SRAM cells considering the statistical distributions of gate length and silicon thickness of its transistors is presented. The corresponding statistical correlations of these two parameters are also considered. In this method, proper back-gate voltages for the SRAM transistors which maximize the yield against read, write,...
In this paper, we propose low power and robust 6T SRAM cells. The cells are based on the Vt-control of the cross-coupled inverters of the SRAM cell to reduce leakage power when SRAM is in the idle mode. Using the Vt-control method along with the built-in feedback leads to increasing the SNM. In comparison to a previous work, our schemes have a higher static noise margin (SNM) and lower standby power...
Quantum-dot cellular automata (QCA) implementation of digital logic circuits families has received popular attention. A QCA circuit because of its unique characteristics in terms of power consumption, speed and size of the circuit could be a great potential alternative for classical circuits. However, control over the timing and fault-tolerance are significant issues in design and manufacturing. This...
In this paper, optical clocking systems are compared to electrical clocking systems. Three symmetrical optical clock distribution patterns, namely, H, X, and Y, are considered. The important factors for the optical distribution network are compared for different detector capacitances and clock tree shapes. The results show that the shape of clock distribution network does not have considerable impact...
In this paper, a static random access memory (SRAM) cell that reduces the gate leakage power with low access latency is proposed. The technique reduces the gate leakage current both in the zero and in the one states. The efficiency of the design is evaluated by simulating the circuit in a 45-nm CMOS technology. Compared to the conventional SRAM cell, the proposed design reduces the total gate leakage...
In this paper, we introduce a topology for network on chips that is named cluster-mesh (CM) topology. This architecture reduces dynamic and static power consumption in NoCs and can reduce latency of communications in low traffic or local traffic applications. With cluster-mesh topology, area reduction in routers is about 44% and in links we can save more than 50% in area too. The dynamic power in...
Issues related to substrate noise in system-on-chip design are described including the physical phenomena responsible for its creation, coupling transmission mechanisms and media, parameters affecting coupling strength, and its impact on mixed-signal integrated circuits. Design guidelines and best practices to minimize the generation, transmission, and reception of substrate noise are outlined, and...
An optimization approach for design of domino logic circuit using genetic algorithm is proposed in this paper. Simulation-based genetic algorithm is used to design of domino logic circuit to achieve a high accurate result. By the given noise margin, delay, leakage power and active power, the fitness function is defined and the genetic algorithm is used to get a proper transistor sizing. The simulation...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.