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In this paper, we present an efficient technique for mapping a set of IP-cores onto tiles of a network-on-chip (NoC). Our constraints are power dissipation, communication bandwidth, and routing resources. To evaluate the proposed scheme, the technique has been applied to some real applications and random task graphs with different sizes of mesh topologies. The results of the mapping technique are...
In this paper, we propose an efficient centralized clustering algorithm for wireless sensor networks. The algorithm which organizes the sensors into clusters uses memetic algorithm to determine cluster heads and sizes. Memetic algorithms which are similar to genetic algorithms are population-based heuristic search approaches for optimization problems. To assess the efficiency of the proposed clustering...
In this paper the speed improvement of a 16times16 multiplier is addressed via sizing of the transistors used in multiplying blocks. Genetic algorithm (GA) is used to calculate the appropriate W for transistors. Modification of W/L ratio of transistors has reduced the multiplier delay up to 16 percent under different supply voltages and technologies with respect to the case of transistors having non-optimized...
In this paper, the optimization of power-delay-product (PDP) of a high-speed flip-flop via transistor sizing is presented. The optimization is performed using the genetic algorithm (GA). The flip-flop which is used in this optimization is called modified hybrid latch flip-flop (MHLFF). The genetic algorithm is implemented in MATLAB with the fitness function expressed in terms of the power and the...
An optimization approach for design of domino logic circuit using genetic algorithm is proposed in this paper. Simulation-based genetic algorithm is used to design of domino logic circuit to achieve a high accurate result. By the given noise margin, delay, leakage power and active power, the fitness function is defined and the genetic algorithm is used to get a proper transistor sizing. The simulation...
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