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In DVE systems, maintaining the consistency of event execution time is the core element to provide a unified view for all nodes in the system. However, owing to the fluctuation of message transmission delay within the network, some events cannot be executed at the expected time set by the sending node., It will seriously impact the interactive experience of the user in the virtual environment, especially...
Library based design and IP reuse have been previously proposed to speed up the synthesis for large-scale FPGA designs. However, previous library based design flow faces several unresolved challenges. Firstly, they may result in large waste area between the modules due to the difference in module sizes. While utilizing multiple ratio modules can help to reduce the waste area, pre-synthesis each module...
This paper investigates the H∞ control design for memristor-based neural networks (MNNs) in the presence of actuator saturation and external disturbance. Initially, using characteristic function technique, we transform a general model of MNNs to a new form to solve the control design problem. Then, by constructing a appropriate Lyapunov function, a constrained H∞ control design is developed to exponentially...
The downlink scheduling is always a key problem in the wireless communication. In time of LTE and 5G, the real time multimedia is demanding more resources and flexibility. To meet this ever growing challenge for the QoE of users, a novel layered scheduler is designed in this paper, which treats the constraint of delay and the object for maximal throughput separately. Taking the fluctuations in both...
Delays often occur in real-world software development projects and may cause significant monetary penalties to software companies. Meanwhile, industry lessons have shown that adding inexperienced employees would cause further delays due to the learning curve and communication overhead. However, if employees with same or similar skills and domain knowledge can be rescheduled from other concurrent projects...
Library based design and IP reuse have been previouslyproposed to speed up the synthesis for large-scale FPGAdesigns. However, previous library based design flow faces severalunresolved challenges. Firstly, there may result in large wastearea between the modules due to the difference in module sizes. While utilizing multiple ratio modules can help to reduce thewaste area, pre-synthesis each module...
Static timing analysis is crucial for design of realtime systems. While the worst-case execution time of a task is typically computed or measured in a single task environment, the presence of caches imposes additional cache related preemption delay (CRPD) cost to the lower priority tasks in a preemptive multi-tasking system. In this work, we show that existing instruction CRPD analysis techniques...
In a Distributed Virtual Environment (DVE) system, a multi-server infrastructure is often used to improve scalability and responsiveness. With this infrastructure, every client needs to be mapped to a proper server, and the mapping result is crucial because it affects the overall system performance and the users' interactive experiences. Existing mapping methods primarily consider the load balancing...
Although wireless sensor networks are widely used in recent years, it remains a big security risk in the transmission of information and energy consumption of the nodes. By summarizing the existing wireless sensor networks attack measures, this paper proposes a way to attack wireless sensor networks by wireless injection, at different times fake nodes is disguised as acquisition nodes and transmission...
In elastic cloud computing environment, multiple virtual machines may reside in the same physical machine for services consolidation. For the same residential guest domains or multi-tiered hosting services, the inter-domain communications are complex and frequent. However, traditional inter-domain communications are conducted through the virtual network interfaces of both sending and receiving virtual...
To minimize the access latency of set-associative caches, the data in all ways are read out in parallel with the tag lookup. However, this is energy inefficient, as only the data from the matching way is used and the others are discarded. This paper proposes an early tag lookup (ETL) technique for L1 instruction caches that determines the matching way one cycle earlier than the cache access, so that...
LTE is an all IP network. The scheduling in its downlink channels is a key problem. Although many algorithms have been designed and analyzed, the QoS for the users in poor channel conditions are not enough to be ensured sometimes. We design a method to enhance the capacity of the system, which is a modifying strategy available for most existing algorithms. Our intuition is to allocate more resources...
The integration of network function virtualization (NFV) and software defined networks (SDN) seeks to create a more flexible and dynamic software-based network environment. The line between entities involved in forwarding and those involved in more complex middle box functionality in the network is blurred by the use of high-performance virtualized platforms capable of performing these functions....
Large on-chip caches with uniform access time are inefficient to be used in multicore processors due to the increasing wire delays across the chip. The Non-Uniform Cache Architecture (NUCA) is proved to be effective to solve the problem of the increasing wire delays in multicore processors. For real-time systems that use multicore processors, it is crucial to bound the worst-case execution time (WCET)...
In this paper, we first propose a static analysis approach to estimate the maximum value of the worst-case latency of all possible communications in a Chip Multi-Processor (CMP) with a 2D-Mesh Network-on-Chip (NoC), which is called the Worst-case Inter-core Communication Latency (WICL). Then the Hop-based Priority scheduling approach is proposed for a 2D-Mesh NoC to improve its WICL. Our experimental...
Large on-chip caches with uniform access time are inefficient to be used in multicore processors due to the increasing wire delays across the chip. The Non-Uniform Cache Architecture (NUCA) is proved to be effective to solve the problem of the increasing wire delays in multicore processors. For real-time systems that use multicore processors, it is crucial to bound the worst-case execution time (WCET)...
As transistor feature size scales down, soft errors in combinational logic because of high-energy particle radiation is gaining increasing concerns. In this paper, a soft error mitigation method based on accurate mathematical modeling of SER and addition of non-invert functionally redundant wires (FRWs) is proposed. In the proposed method, the factors which have significant influences on SER because...
This paper investigates stability and stabilization of positive switched systems under asynchronous switching, which means that the switching of the controller has a delay to that of the system mode. First, two sufficient conditions for the stability of autonomous systems are established. The first one is obtained by using the linear copositive Lyapunov function incorporated with linear programming...
Reconfigurable architectures, such as Field-Programmable Gate Arrays (FPGAs), have become one of the key digital circuit implementation platform over the last decade due to its short time-to-market and low design cost. However, the major bottlenecks of FPGAs are their low logic utilization rate and long reconfiguration latency. In order to overcome these limitations, novel dynamically reconfigurable...
We consider the stabilization of discrete-time nonlinear OdE systems under discrete transport PdEs which convect in opposite directions. An explicit feedback law that compensates discrete transport PdEs actuator dynamics is designed. Global asymptotic stability of the closed-loop system is proved with the aid of a Lyapunov function. The feedback design is illustrated through an example. The proposed...
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