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This paper presents an HDTV video decoder core that is able to decode MPEG-2, MPEG-4 AVC and VC-1 formats and is fully compatible with the Blu-ray Disc standard. The core has two major features which achieve low-cost hardware implementation for three different standards. First, a novel re-configurable architecture is adopted to realize reduced hardware for three different variable length coding tables...
This paper proposes a circuit structure which can improve signal-to-noise ratio of a conventional common-gate CMOS LNA for UWB (Ultra-Wide-Band; 3.1-10.6 GHz) using 0.18 um CMOS technology. The simulated results show that the proposed circuit has gain of 16.3-18.8 dB and NF of less than 3dB as well as good compatibility with input matching in a wide frequency range needed in UWB, and it consumes 16...
A AAC-decoding, H.264 decoding, media processor with embedded forward-body-biasing and power-gating circuit in CMOS technology is proposed. Since all the components necessary for the scheme are simple MOS circuits requiring no extra supply voltages, they can be placed and routed by a commercial CAD tool. A data-mapping flip-flop was proposed as a high performance and low-power flip-flop. It is concluded...
This paper presents an HDTV video decoder core that is is able to decode MPEG-2, MPEG-4 AVC and VC-1 formats and is fully compatible with the Blu-ray Disc standard. A novel re-configurable architecture is adopted to achieve reduced hardware, and a data compression method suitable for all video decoding standards is applied to reduce memory data usage and access bandwidth. The circuit volume of the...
A novel complementary quadrature LC oscillator is presented for achieving lower phase noise. One proposed and three conventional structures, designed in a 0.18 mum CMOS technology, are simulated in both the triple-well and the twin-well (exactly the quasi twin-well) process technologies and each phase noise is compared. These circuits operate at 5 GHz and draw 8.6 mA from a 1.8 V supply. In the triple-well...
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