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Performance of a double-gate (DG) FinFET in the cryogenic environment is discussed based on measurements and simulation. It was found that the DG FinFET has an excellent immunity to the kink effect in the cryogenic environment. Our physics-based compact model reproduced the measured I–V characteristics. The successful demonstration of an opamp consisting of the DG FinFETs at 4.2 K is also presented.
This paper presents a method to salvage malfunctioned bits in a FinFET SRAM array caused by random threshold voltage (Vt) variation. The Vt of pass gates (PGs) is gradually lowered during the read process from the initial high value until the stored data is detected by the sense amplifier. As a result, the best Vt is automatically chosen for each cell and malfunctioned bits of both those too fast...
This paper presents a novel low voltage LDMOS structure with low on-resistance based on 0.13 μm CMOS technology. 8 V/9 V Nch LDMOS have only 0.3 μm gate length when the maximum gate operating voltage is 5 V, while the gate length of 5 V CMOS is 0.6 μm to avoid the short channel effect. The obtained specific on-resistance are 1.8 mΩmm2 (8 V Nch LDMOS) and 5.9 mΩmm2 (8 V Pch LDMOS) respectively. Furthermore...
A FinFET compact model, which provides physical representation of measurement data, was developed and was successfully applied to the characterization of sate-of-the-art metal-gate (MG) FinFETs. By combining the transistor size measurement and the model parameter calibration, the Vth variation of the MG FinFETs was analyzed into structure-based (TSi, LG) and material-based (gate work-function) variations...
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