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A novel SOI LDMOS with Double Trench Gate (DTG) is proposed. The DTG SOI LDMOS is obtained by introducing an additional trench gate between P-well region and N-drift region, which can form one more n-channel in on-state. The parameters of DTG SOI LDMOS were optimized to some extend through 2D device simulations and some main electronic properties were obtained through 2D device simulation with Silvaco...
The simulated cross section of vertical gate RF SOI LIGBT with TCAD ATHENA is illustrated in Fig. 8 by using the constrains of advanced SOI CMOS VLSI technologies, which demonstrates that the proposed device cell structure is feasible in technology with advanced SOI CMOS VLSI technologies. The primarily simulated current-voltage characteristics of RF SOI LDMOS/LIGBT cell does not latch-up at VGS=2...
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