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This paper designed a 1-Mb HfOx-based embedded Resistive Random Access Memory (RRAM) device with a one-transistor-one-resistor (1T1R) structure, and systematically investigated its working temperature range. It noted that this embedded RRAM macro has a 1.6X working temperature range than previous design for some extreme environment. Using the peripheral-assisted technique, it can enable the error...
Recent advances in the Internet-of-Things has given rise to the possibility of connecting different kinds of devices to the internet. With low computing resources constraining most IoT devices and their networks, managing the capabilities and services of the various constrained devices over the internet has been an issue for IoT implementations. Existing approaches to this problem lack end-to-end...
We investigated the endurance characteristics of a Cu-doped HfO2 selector device in one transistor-one selector (1T1S) structure, which is fully compatible with standard BEOL process. The device exhibits high endurance of 1010 under 10 μΑ compliance current. However, reduced endurance (105) was observed as increasing the compliance up to 100 μΑ. Under the condition of high operation, intrinsic defect...
Motivated by reduction of computational complexity, this work develops a pipelined adaptive filter architecture using the sign-error least mean square (SELMS) algorithm. The proposed algorithm was implemented with less than half the amount of calculation consumed for the conventional architectures. Besides, the proposed designs derived by retiming technique and with low latency also provide a faster...
Passive Optical Network (PON) is the most promising technology in optical access network, and the effective and reasonable upstream dynamic bandwidth allocation (DBA) is the key. This paper proposes a new software defined WDM-TDM PON frame that enable more users to share a single high-capacity fiber access as well as introduce a flexible DBA module to replace the hardware-configured DBA module. The...
This paper presents a programmable lab-on-CMOS (LoCMOS) with micro-electrode cell array. Array structure is suitable for programmable like CMOS VLSIs. In order to improve the utilization, each micro-electrode cell is composed of actuation and sensing circuit. In addition, a CMOS-compatible extended drain MOSFET (EDMOS) is adopted under a 3V supply. This LoCMOS platform is composed of 1,800 microelectrodes...
NAND flash is seeing increasing adoption in the data center because of its orders of magnitude lower latency and higher bandwidth compared to hard disks. However, flash performance is often degraded by (i) inefficient storage I/O stack that hides flash characteristics under Flash Translation Layer (FTL), and (ii) long latency network protocols for distributed storage. In this paper, we propose a minimalistic...
A 4K and Main-10 HEVC video decoder LSI is fabricated in a 28nm CMOS process. It adopts a block-concealed processor (BcP) to improve the visual quality and a bandwidth-suppressed processor (BsP) is newly designed to reduce 30% and 45% of external data accesses in playback and gaming scenario, respectively. It features fully core scalable (FCS) architecture which lowers the required working frequency...
We propose improving system availability by performing in-field repair at the chip level. This enables margining and detection of degrading memory cells before the user observes any errors. A 576 Mb embedded DRAM at 1.5 GHz in a 40nm CMOS technology achieves improved resilience to both aging memory cells and cells with variable retention time (VRT). Un-interrupted user access of 6 billion 72-bit read...
1T1R-architecture devices were fabricated by integrating ZrO2 based crossbar structure ReRAM onto a foundry-built MOSFET platform. Multilevel operation was realized by using the current limit of a selected cell transistor in the set process. The current level was determined by the transistor's gate voltage, resulting in the control of electrical resistance of the filamentary conductive paths in the...
in this paper, a new flexible VLSI architecture of H.264/AVC decoder is presented. The proposed design implementation can get a good performance result as fully pipelined construction.
An ATCA-based computation platform for data acquisition and trigger (TDAQ) applications has been developed for multiple future projects such as PANDA, HADES, and BESIII. Each Compute Node (CN) appears as one of the fourteen Field Replaceable Units (FRU) in an ATCA shelf, which in total features a high performance of 1890 Gbps inter-FPGA onboard channels, 1456 Gbps inter-board backplane connections,...
In this paper we use software engineering methods and Shannon's communication model to investigate computer network architecture. We get a new type of computer network architecture and some significant conclusions. At the first phase of the life cycle of software engineering, that is, requirement analysis, we get a series of unexpected conclusions. For example, a variety of computer network architectures...
Traditional e-business focuses on physical products trading, and although there are transactions of the so called "virtual products", its scope is limited to "downloadable files" or game card points. But in offline market, services & intellectual works forms an important part in all commercial fields. By reconstructing the concept of "intangible product" in e-business...
In particle physics experiments, the momenta of charged particles are studied by observing their deflection in a magnetic field. Dedicated detectors measure the particle tracks and complex algorithms are required for track recognition and reconstruction. This CPU-intensive task is usually implemented as off-line software running on PC clusters. In this paper, we present a system-on-chip design for...
In this paper, novel reconfigurable architectures are introduced to utilize high-density resistive memory (RRAM) to build FPGA components. Different from the existing CMOS-nano hybrid circuits that use crossbars, the proposed rFPGA structures consist of mainly 1T1R structures (1 CMOS transistor is integrated with a two-terminal resistive nanojunction) that can be fabricated using a CMOS-compatible...
This paper deals with the behavior control strategy of autonomous robots. Since conditioned reflex and emotions make living things intelligent to adapt to different environments, they are combined with each other in the presented strategy to endow the robot with the ability of adapting to various conditions. The associative memory is also used to enhance the learning efficiency. Simulation results...
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