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A 10-b low-voltage CMOS pipelined analog-to-digital converter is described. A low-voltage technique is proposed for pipelined ADC that avoids the use of low-threshold voltage process, on-chip clock voltage doubler, bootstrapped switch, or switched-opamp technique. At the front-end, a low-voltage S/H circuit with cross-coupled input sampling switch is employed to eliminate the input signal feedthrough...
Two fully differential CMOS 1V switched-capacitor amplifiers in a standard CMOS 0.35 mu m technology are presented. The improved bootstrapped switches are used to allow rail-to-rail signal swing. The circuit design of major building blocks is described. The performance of these two circuits is demonstrated by experimental results.
A new technique for realizing a very-high-speed low-power low-voltage CMOS fully differential track-and-hold circuit with low hold pedestal is presented. To achieve high sampling linearity the circuit utilizes improved bootstrapped input switch. The fully differential design relaxes the trade-off between sampling speed and the sampling precision. The circuit design of major building blocks is described...
A 10-bit 60-MS/s low-power CMOS pipelined analog-to-digital converter (ADC) is proposed. At the front-end, a timing-skew-insensitive double-sampled Miller-capacitance-based sample-and-hold circuit is employed to enhance the dynamic performance of the pipelined ADC. Bootstrapped switch achieves rail-to-rail signal swing at low-voltage power supply. Employing double sampling and bias current scaling...
A new technique for realizing a very-high-speed low-power low-voltage fully differential CMOS track-and-hold circuit with low hold pedestal is presented. To achieve high sampling linearity the circuit utilizes bootstrapped input switch. The fully differential design relaxes the trade-off between sampling speed and the sampling precision. The circuit design of major building blocks is described in...
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