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A novel on-chip process-variation monitoring circuit for nanoscale CMOS designs is proposed. The proposed circuit can monitor both global and local variations associated with transistors on an integrated circuit. The process variation is monitored by gate-tunnelling-leakage sensing with weak temperature dependence, which solves the problem of the strong temperature dependence of the conventional subthreshold...
This paper describes a design and implementation of low-power and high-speed security hardware cores for the advanced encryption standard (AES) and the secure hash algorithm (SHA1). We propose three register transfer level (RTL) circuit techniques, namely, application specific register reduction (ASRR), locally explicit clock enabling (LECE), and bus specific clock (BSC). LECE and BSC can be used...
In this paper, we propose a RT level power reduction scheme which can be used for any applications that have power problem when designers use traditional design flow. A novel wasting-toggle-rate based clock power reduction technique is introduced and verified along with traditional design flow. The proposed technique can choose optimal clock-gating style selectively to minimize the power based on...
This paper proposes a new method for switching the capacitors in the DAC capacitor array of a successive approximation register (SAR) ADC. By separating the decoding of the most significant bits and the least significant bits, and using two different capacitor arrays with unequal size to determine their values, respectively, the average switching energy of the capacitor arrays can be dramatically...
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