The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
IC backend chip scale package Re-Distribution Layer (RDL) routing space is getting smaller and pattern density is getting higher while device technology has been scaling down continuously. However, smaller routing space will induce higher leakage current due to higher occurrence of metal residue remaining. Higher metal density will also induce poor 2 polymer films adhesion and cause higher failure...
Pd has long been used as a high efficient catalyst for hydrogen dissociation and absorption. Pd thin films of few nm thickness are widely used in metal-hydride systems. In the Pd-alloys, the hydroge-nation of Pd may easily bring in proximity effect upon the underneath functional materials. This effect is important from fundamental point of view and also applicable in future techniques. Besides of...
We present a fully-integrated SOI CMOS 22nm technology for a diverse array of high-performance applications including server microprocessors, memory controllers and ASICs. A pre-doped substrate enables scaling of this third generation of SOI deep-trench-based embedded DRAM for a dense high-performance memory hierarchy. Dual-Embedded stressor technology including SiGe and Si:C for improved carrier...
Device scaling is critical for continuing trend of more functionality in a chip. Traditional planar CMOS scaling is increasingly difficult due to limitations in processing and material properties, device structure and reliability. In this paper we will summarize recent advances in these areas, which will enable technology scaling as per Moore's law.
Wafer-scale-assembly (WSA) technology has been developed for compact and light-weight applications at the Northrop Grumman Corporation. To insure successful insertion of WSA hermetic MMICs for military and space applications, high-reliability demonstration is essential. In this study, we performed two-temperature lifetesting to evaluate the reliability performance of WSA hermetic GaAs HEMT MMICs....
The temperature dependence of device performance is a critical factor that determines overall product power-performance. We show HKMG gate stacks drive significantly higher threshold temperature dependence over poly-Si/SiON. We further show that in SOI, the work-function engineering enabled by HKMG integration schemes can result in even higher Vt temperature sensitivity attributed to differences in...
The authors have successfully demonstrated self-aligned high-performance inversion-channel In0.53Ga0.47As MOSFETs using UHV-deposited nano-meter thick AI2O3/GGO dual-layer dielectrics and a TiN metal gate. Record-high drain current and transconductance, despite its challenging process, were achieved. Ring gate D-mode In0.2Ga0.8As MOSFETs using as a similar dual layer gate dielectric also exhibits...
Northrop Grumman space technology (NGST) is developing advanced InP-based HBT microelectronics for next generation high performance aerospace, defense and commercial applications. In this paper we describe these production and advanced technologies including a 0.25 um InP HBT. We present device description, performance, and circuit demonstrations for these technologies.
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.