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In this paper, we propose a novel 24-transistor change-sensing flip-flop (CSFF) for ultra-low power applications. With the aid of an internal change-sensing unit, the proposed CSFF eliminates redundant transitions of internal clocked nodes when there is no change in the flip-flop content. No additional transistors are required compared to the conventional transmission-gate flip-flop (TGFF). Measurement...
Ring oscillator based test structures that can separately measure the NBTI and PBTI degradation effects in digital circuits are presented for high-k metal-gate devices. The proposed test structures enable simultaneous stress of all devices under test in either NBTI or PBTI mode and measure frequency or threshold voltage shifts. The mathematical derivation also shows that the structure for frequency...
We report on the resistive switching mechanism of dc magnetron sputtered hafnium-silicates (HfxSi1-xO2) memory thin films. It is observed that the electroforming of these films depends on the thickness and stoichiometry of the insulator as well as on the size of the top electrode (TE). Both high-conducting state (ON) and low-conducting state (OFF) are non-polar and stable. The ratio of resistance...
AC-DC transfer standard and micro-potentiometer are widely used for AC voltage standard at low level. Input impedance and 50-Ω load dependency of the standard are discussed for the ac voltage application below 200 mV and 1 MHz. The load dependency of the unit reaches 385 μV/V at 1 MHz, and this loading error should be corrected when calibrate the 50-Ω AC source using the standard.
A semi-active high-efficient (SA-HE) CMOS rectifier with reverse leakage control has been developed. It employs a cross-coupled NMOS pair and two leakage control comparators to reduce reverse charge leakage current. In addition, the adaptive body bias control technique is utilized to improve the reliability of the rectifier. The SA-HE rectifier has been fabricated in a 0.18um CMOS technology and shows...
Negative Bias Temperature Instability (NBTI) is one of the most critical device reliability issues facing scaled CMOS technology. In order to better understand the characteristics of this mechanism, accurate and efficient means of measuring its effects must be explored. In this work, we describe an on-chip NBTI degradation sensor using two delay-locked loops (DLL). The increase in PMOS transistor...
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