The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
TSV-induced stress is an important issue in 3D IC design since it leads to serious reliability problems and influences device performance. Existing finite element method can provide accurate analysis for the stress of simple TSV placement, but is not scalable to larger designs due to its expensive memory consumption and high run time. On the contrary, linear superposition method is efficient to analyze...
The 3D IC integration using through-silicon-vias (TSV) has gained tremendous momentum recently for industry adoption. However, as TSV involves disruptive manufacturing technologies, new modeling and design techniques need to be developed for 3D IC manufacturability and reliability. In particular, TSVs in 3D IC may cause significant thermal mechanical stress, which not only results in systematic mobility/performance...
In this work, we propose a fast and accurate chip/package thermo-mechanical stress and reliability co-analysis tool for TSV-based 3D ICs. We also present a design optimization methodology to alleviate mechanical reliability issues in 3D IC. First, we analyze the stress induced by chip/package interconnect elements, i.e., TSV, μ-bump, and package bump. Second, we explore and validate the principle...
In this work, we propose an efficient and accurate full-chip thermo-mechanical stress and reliability analysis tool and design optimization methodology to alleviate mechanical reliability issues in 3D ICs. First, we analyze detailed thermo-mechanical stress induced by TSVs in conjunction with various associated structures such as landing pad and dielectric liner. Then, we explore and validate the...
As the geometry shrinking faces severe limitations, 3D wafer stacking with through silicon via (TSV) has gained interest for future SOC integration. Since TSV fill material and silicon have different coefficients of thermal expansion (CTE), TSV causes silicon deformation due to different temperatures at chip manufacturing and operating. The widely used TSV fill material is copper which causes tensile...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.